(a) Field of the Invention
The present invention relates to a drive circuit for a LCD (liquid crystal display) device and, more particularly, to a drive circuit for an active matrix LCD device. The present invention also relates to a LCD device having such a drive circuit.
(b) Description of the Related Art
Recently, active matrix LCD devices having a TFT (thin film transistor) and a storage capacitor in each pixel element are increasingly used. FIG. 1 shows a general configuration of a conventional active matrix LCD in a block diagram.
The LCD device has a plurality of data lines 531 extending parallel to one another in a column direction, a plurality of gate lines 532 extending parallel to one another in a row direction, and a pixel matrix 53 including a plurality of pixel elements arranged in a matrix and each disposed in the vicinity of cross points of the data lines 531 and the gate lines 532.
Each pixel element includes therein a TFT 533 having a source connected to a corresponding data line 531 and a gate connected to a corresponding gate line 532, and a storage capacitor 534 connected between the drain of the TFT 533 and the ground. Each data line 531 and each gate line 532 are connected to a data driver 51 and a gate driver 52, respectively, of a LCD drive circuit disposed for the LCD panel. The data driver 51 receives a video signal Vsig in addition to a starting pulse SPd and a clock signal .phi.d from a control circuit 50 to output portions of the video signal Vsig through respective data lines 531 during each horizontal scanning period, whereas the gate driver 52 receives a starting pulse SPg and a clock signal .phi.g to select gate lines 532. The data driver 51 includes a scanning circuit, and a plurality of drive sections each disposed for a corresponding data line, each of the drive sections including a sample/hold circuit and an output circuit. The gate driver 52 includes a scanning circuit for consecutively selecting the gate lines 532 one by one during each vertical scanning period or frame period.
FIG. 2 shows a signal timing chart in the LCD device of FIG. 1. When the scanning circuit of the data driver 51 starts for scanning after receiving a starting pulse SPd from the control circuit 50, a video signal Vsig for a single horizontal line of the LCD panel supplied from the control circuit 50 is sampled in the data driver 51 in synchrony with a clock signal .phi.d. That is, portions of the video signal Vsig for the single horizontal line are consecutively sampled and held by respective sample/hold circuits during the horizontal scanning period, and are output at the next horizontal scanning period through respective output circuits and data lines 531. The gate driver 52 starts for scanning after receiving a starting pulse SPg to select the gate lines 532 one by one during a vertical scanning period. By these operations, video signals are written into the pixel elements row by row, and stored by the respective storage capacitors to form a single frame in each frame period.
FIG. 3 shows an exemplified configuration of each drive section 51A of the data driver 51, whereas FIG. 4 shows a signal timing chart of the drive section of FIG. 3. The drive section of FIG. 3 is disposed for a single data line 531, and includes a sample/hold circuit 55 and an output circuit 56. The sample/hold circuit 55 includes switches 61 and 63 and first and second storage capacitors 62 and 64, and the output circuit 56 is implemented by a source follower.
The input node Vin of the drive section 51A is connected to the input terminal of the data driver 51, which in turn is connected to a video signal line. Switch 61 is closed by a scanning signal SMa supplied from the scanning circuit, to receive a portion of the video signal Vsig supplied at that time corresponding to the specific data line 531, thereby storing the signal portion on a first storage capacitor 62. After the scanning circuit scans one horizontal line during a single horizontal period, switch 63 together with other corresponding switches for other data lines is closed by a control signal SMb at the same time to shift the signal portion from the first storage capacitor 62 to a second storage capacitor 64, together with corresponding other signal portions of the video signal supplied during the horizontal period. The video signal portion stored on the second storage capacitor 64 is supplied to the data line 531 as an output video signal Vout during the next horizontal period together with other signal portions to form a single frame image.
In a LCD device, the video signal Vsig has a large amplitude of 5 to 12 volts, for example, and also it is required for the output circuit to effect a quick charge and quick discharge of the data line within tens of micro seconds. The load capacitance CL of the drive section 51A is a sum of the pixel capacitor 534 and the parasitic capacitance of the data line 531. The frequency characteristics of the output circuit are determined by a time constant, which is defined by the load capacitance and the on-resistance of the transistor 65 during a charge period of the data line and by the load capacitance and the load resistance 66 during a discharge period of the data line. Thus, in order for improvement of the frequency characteristics of the output circuit, it is desired to reduce the on-resistance of the transistor 65 and the load resistance 66.
However, if the load resistance 66 is to be reduced to obtain a sufficient frequency characteristics of the output circuit, there arises a problem in that a penetrating current increases which flows from the high potential source line VH to the low potential source line VL at any time through the transistor 65 and the load resistance 66. The penetrating current flowing even after completion of the charge and discharge of the data line involves a large power dissipation in the driver circuit 51 of the LCD device.
Especially in the case of a drive circuit disposed on a common glass substrate together with the pixel matrix, it is known that radiation through the glass substrate is extremely low to thereby cause a temperature rise in the drive circuit, raising a critical thermal problem therein.
There is a solution of the above problem in JP-B-2(1990)-10436. The proposed drive circuit, as shown in FIG. 5, includes a switch 68 in the output circuit in place of the load resistor 66 shown in FIG. 3, and additionally a switch 69 connected between the gate of the output transistor 65 and a low level voltage source VRL. Referring additionally to FIG. 6 showing a signal timing chart in the proposed drive circuit, before transferring a video signal portion from the first capacitors 62 to the second capacitors 64, switches 69 are closed by a control signal RSTg to set the gate voltage Vg of the output transistors 65 at a low level VRL, thereby turning off the transistors 65. During the period when the output transistors 65 are off, switches 68 are closed by control signal RSTd to discharge the data lines, thereby setting the output nodes Vout at a low level VL
After switches 67 and 68 are opened by a low level of control signals RSTg and RSTd, the video signal is transferred from the first capacitors 62 to the second capacitors 64 by control signal SMb so that each output transistor 65 charges the load capacitor 67 to a voltage level corresponding to the gate voltage thereof. Here, each output voltage Vout is defined by the threshold voltage Vt and the gate voltage Vg of each output transistor 65 as follows: EQU Vout=Vg-Vt (1)
After the load capacitor 67 is charged to the voltage level Vout defined by equation (1), the output transistor 65 is turned off to cut the charge current. Thus, the penetrating current flowing from the high voltage source line VH to the low voltage source line VL through the output transistor 65 in the conventional drive circuit is removed, thereby reducing the power dissipation.
In the proposed drive circuit, the output node Vout is connected to the source of the output transistor 65. Accordingly, even if the gate voltage Vg is lowered in order to decrease the potential of the output node Vout, the potential of the output node Vout cannot be lowered in the case of relationship Vg-Vout&lt;Vt due to the off state of the output transistor 65. That is, switch 68 must be closed to discharge the load 67 for lowering the potential of the output node to a low level VL at every horizontal period. The low level VL is lower than the lowest level applied to the liquid crystal, and the discharge of the output node Vout to this lower level VL again involves a significant power dissipation.